Field of the Invention
The present invention is directed to a method for manufacturing neighboring wells implanted with dopants of different conductivity types as are used for the manufacture of p-channel or n-channel or bipolar transistors in LSI CMOS circuits, the wells being arranged in a common semiconductor substrate and being separated by insulating trenches introduced into the substrate.
An adequate latch-up strength can no longer be achieved with a traditional LOCOS insulation in view of further miniaturization of CMOS components in ULSI technology (ultra large scale integration). The insulating means around the wells must be produced by etching and filling deep and narrow trenches. On the other hand, the insulating ridges within the wells should continue to remain flat in order to assure a good electrical contacting of the overall well with minimum well contact density. Two separate insulating processes are therefore needed in this technology. The process becomes more involved due to an additional photomask step for the trench etching. The adjustment tolerances also limit the amount of minitaturization possible.
In order to eliminate the additional photo technique, Sujama et al. in a report appearing in IEEE Transactions on Electron Devices, Vol. ED-33, No. 11, November, 1986, pages 1672 to 1677 propose that the well mask be employed in order to manufacture a self-adjusting aluminum mask for the trench etching in a lift-off technique. The disadvantages of this method are the stresses on the silicon substrate due to the aluminum mask, the metal contamination due to employment of aluminum in this early process stage and the appearance of high particle density due to the aluminum lift-off. Moreover, this process only permits one well implantation and a self-adjusting well process is not possible with this process.